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?2003 integrated device technology, inc. april 2003 dsc-4859/3 1 functional block diagram features: true dual-ported memory cells which allow simultaneous access of the same memory location high-speed clock to data access ? commercial: 6/7.5/9/12ns (max.) ? industrial: 9ns (max.) low-power operation ? idt70v9199/099l active: 500mw (typ.) standby: 1.5mw (typ.) flow-through or pipelined output mode on either port via the ft /pipe pins dual chip enables allow for depth expansion without additional logic counter enable and reset features full synchronous operation on both ports ? 3.5ns setup to clock and 0ns hold on all control, data, and address inputs ? data input, address, and control registers ? fast 6.5ns clock to data out in the pipelined output mode ? self-timed write allows fast cycle time ? 10ns cycle time, 100mhz operation in pipelined output mode lvttl- compatible, single 3.3v (0.3v) power supply industrial temperature range (?40c to +85c) is available for selected speeds available in a 100-pin thin quad flatpack (tqfp) idt70v9199/099l 0 1 0/1 1 0/1 0 r/ w r oe r ce 0r ce 1r ft /pipe r i/o control memory array counter/ address reg. i/o control 4859 drw 01 a 16r a 0r clk r ads r cnten r cntrst r a 0l clk l ads l a 16l cnten l cntrst l counter/ address reg. r/ w l ce 0l oe l ce 1l i/o 0l - i/o 8l (1) i/o 0r -i/o 8r (1) . 1 0/1 0 0 1 0/1 ft /pipe l high-speed 3.3v 128k x9/x8 synchronous pipelined dual-port static ram note: 1. i/o 0 x - i/o 7 x for idt70v9099.
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 2 index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 v s s gnd ft /pipe r oe r r/ w r cntrst r ce 1r ce 0r nc nc v ss a 12r a 13r a 11r a 10r a 9r a 8r a 7r nc nc a 14r nc nc 4859 drw 02 nc nc ft /pipe l oe l r/ w l cntrst l ce 1l ce 0l nc nc nc v dd a 14l a 13l a 8l a 7l nc nc nc a 12l a 11l a 10l a 9l i / o 6 r i / o 5 r i / o 4 r i / o 3 r i / o 2 r i / o 0 r i / o 0 l i / o 1 l v s s i / o 2 l i / o 4 l i / o 5 l i / o 6 l i / o 7 l i / o 3 l i / o 1 r i / o 7 r i / o 8 l i / o 8 r a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 r c n t e n r c l k r a d s r a d s l c l k l c n t e n l a 0 l a 2 l a 3 l a 5 l a 6 l a 1 l a 4 l n c n c v d d v s s v d d v s s v s s n c n c n c 70v9199pf pn100-1 (4) 100-pin tqfp top view (5) a 15r a 16r a 15l nc a 16l . 04/02/03 description: the idt70v9199/099 is a high-speed128k x9/x8 bit synchronous dual-port ram. the memory array utilizes dual-port memory cells to allow simultaneous access of any address from both ports. registers on control, data, and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows systems to be designed with very short cycle times. pin configuration (1,2,3) notes: 1. all v dd pins must be connected to power supply. 2. all v ss pins must be connected to ground supply. 3. package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. with an input data register, the idt70v9199/099 has been optimized for applications having unidirectional or bidirectional data flow in bursts. an automatic power down feature, controlled by ce 0 and ce 1, permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 500mw of power.
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 3 index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1009998979695949392 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 nc v ss ft /pipe r oe r r/ w r cntrst r ce 1r ce 0r nc nc v ss a 12r a 13r a 11r a 10r a 9r a 8r a 7r nc nc a 14r nc nc 4859 drw 02a nc nc ft /pipe l oe l r/ w l cntrst l ce 1l ce 0l nc nc nc v dd a 14l a 13l a 8l a 7l nc nc nc a 12l a 11l a 10l a 9l i / o 6 r i / o 5 r i / o 4 r i / o 3 r i / o 2 r i / o 0 r i / o 0 l i / o i l v s s i / o 2 l i / o 4 l i / o 5 l i / o 6 l i / o 7 l i / o 3 l i / o 1 r i / o 7 r n c n c a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 r c n t e n r c l k r a d s r a d s l c l k l c n t e n l a 0 l a 2 l a 3 l a 5 l a 6 l a 1 l a 4 l n c n c v d d v s s v d d v s s n c n c v s s n c n c a 15r a 16r a 16l a 15l 70v9099pf pn100-1 (4) 100-pin tqfp top view (5) 04/04/03 pin configuration (1,2,3) (con't.) notes: 1. all v dd pins must be connected to power supply. 2. all v ss pins must be connected to ground. 3. package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking.
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 4 notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ads , cnten , cntrst = x. 3. oe is an asynchronous input signal. 4. i/o 0 - i/o 7 for idt70v9099. truth table i?read/write and enable control (1,2,3) pin names left port right port names ce 0l, ce 1l ce 0r, ce 1r chip enables r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 16l a 0r - a 16r address i/o 0l - i/o 8l (1) i/o 0r - i/o 8r (1) data input/outp ut clk l clk r clock ads l ads r address strobe enable cnten l cnten r counter enable cntrst l cntrst r counter reset ft /pipe l ft /pipe r flow-through / pipeline v dd power (3.3v) v ss ground (0v) 4859 tbl 01 oe clk ce 0 ce 1 r/ w i/o 0-8 (4) mode x h x x high-z deselected?power down x x l x high-z deselected?power down x lhl data in write l lhh data out read h x l h x high-z outputs disabled 4859 tbl 02 truth table ii?address counter control (1,2) notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ce 0 and oe = v il ; ce 1 and r/ w = v ih . 3. outputs configured in flow-through output mode; if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ads and cntrst are independent of all other signals including ce 0 and ce 1 . 5. the address counter advances if cnten = v il on the rising edge of clk, regardless of all other signals including ce 0 and ce 1 . note: 1. i/o 0 x - i/o 7 x for idt70v9099. external address previous internal address internal address used clk ads cnten cntrst i/o (3) mode xx 0 xx l (4) d i/o (0) counter reset to address 0 an x an l (4) xhd i/o (n) external address loaded into counter an ap ap hh h d i/o (p) external address blocked?counter disabled (ap reused) xapap + 1 h l (5) hd i/o (p+1) counter enabled?internal address generation 4859 tbl 03
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 5 dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v 0.3v) note: 1. at v dd < 2.0v input leakages are undefined. recommended operating temperature and supply voltage (1) recommended dc operating conditions absolute maximum ratings (1) notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o . capacitance (1) (t a = +25c, f = 1.0mh z ) notes: 1. v il > -1.5v for pulse width less than 10 ns. 2. v term must not exceed v dd +0.3v. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd +0.3v for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > v dd + 0.3v. 3. ambient temperature under dc bias. no ac conditions. chip deselect. notes: 1. this is the parameter t a . this is the "instant on" case temperature. grade ambient temperature (2) gnd v dd commercial 0 o c to +70 o c0v3.3v + 0.3v industrial -40 o c to +85 o c0v 3.3v + 0.3v 4859 tbl 04 symbol parameter min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v v ss ground 0 0 0 v v ih inp ut high voltag e 2.0 ____ v dd +0.3v (2) v v il inp ut lo w voltage -0.3 (1) ____ 0.8 v 4859 tbl 05 symbol rating commercial & industrial unit v term (2) terminal voltage with resp e ct to gnd -0.5 to +4.6 v t bias (3) te m p e r a tu r e under bias -55 to +125 o c t stg storage te m p e r a tu r e -65 to +150 o c t jn junction temperature +150 o c i out dc output current 50 ma 4859 tbl 06 symbol parameter conditions (2 ) max. unit c in input capacitance v in = 3dv 9 pf c out (3) output capacitance v out = 3dv 10 pf 4859 tbl 07 symbol parameter test conditions 70v9199/099l unit min. max. |i li | input leakage current (1) v dd = 3.6v, v in = 0v to v dd ___ 5a |i lo | output leakage current ce = v ih or ce 1 = v il , v out = 0v to v dd ___ 5a v ol output low voltage i ol = +4ma ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ v 4859 tbl 08
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 6 dc electrical characteristics over the operating temperature supply voltage range (3) (v dd = 3.3v 0.3v) notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions" at input levels of gnd to 3v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 3.3v, t a = 25c for typ, and are not production tested. i dd dc (f=0) = 90ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v dd - 0.2v ce x > v dd - 0.2v means ce 0x > v dd - 0.2v or ce 1x < 0.2v "x" represents "l" for left port or "r" for right port. 70v9199/099l6 com'l only 70v9199/099l7 com'l only 70v9199/099l9 com'l & ind 70v9199/099l12 com'l only symbol parameter test condition version typ. (4) max. typ. (4) max. typ. (4) max. typ. (4) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled, f = f max (1) com'l l 220 280 200 250 175 230 150 200 ma ind l ____ ____ ____ ____ 180 240 ____ ____ i sb1 standby current (both ports - ttl level inputs) ce l = ce r = v ih f = f max (1) com'l l 60 85 50 75 40 65 30 50 ma ind l ____ ____ ____ ____ 50 70 ____ ____ i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (1) com'l l 145 185 130 165 110 145 95 130 ma ind l ____ ____ ____ ____ 110 155 ____ ____ i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v dd - 0.2v, v in > v dd - 0.2v or v in < 0.2v, f = 0 (2) com'll0.420.420.420.42 ma ind l ____ ____ ____ ____ 0.4 2 ____ ____ i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v dd - 0.2v (5) v in > v dd - 0.2v or v in < 0.2v, active port, outputs disabled, f = f max (1) com'l l 145 180 130 160 100 140 90 125 ma ind l ____ ____ ____ ____ 100 155 ____ ____ 4859 tbl 09
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 7 ac test conditions figure 1. ac output test load. figure 2. output test load (for t cklz , t ckhz , t olz , and t ohz ). *including scope and jig. figure 3. typical output derating (lumped capacitive load). 4859 drw 04 590 ? 30pf 435 ? 3.3v data out 590 ? 5pf* 435 ? 3.3v data out 4859 drw 03 1 2 3 4 5 6 7 8 20 40 100 60 80 120 140 160 180 200 tcd 1 , tcd 2 (typical, ns) capacitance (pf) 4859 drw 05 -1 0 - 10pf is the i/o capacitance of this device, and 30pf is the ac test load capacitance . input pulse le vels input ris e/fall time s input timing re fe rence le vels output reference levels output load gnd to 3.0v 3ns max. 1.5v 1.5v figures 1, 2, and 3 4859 tbl 10
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 8 ac electrical characteristics over the operating temperature range (read and write cycle timing) (3) (v dd = 3.3v 0.3v, t a = 0c to +70c) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). this parameter is guarant eed by device characterization, but is not production tested. 2. the pipelined output parameters (t cyc2 , t cd2 ) apply to either or both the left and right ports when ft /pipe = v ih . flow-through parameters (t cyc1 , t cd1 ) apply when ft /pipe = v il for that port. 3. all input signals are synchronous with respect to the clock except for the asynchronous output enable ( oe ), ft /pipe r , and ft /pipe l . 70v9199/099l6 com'l only 70v9199/099l7 com'l only 70v9199/099l9 com'l & ind 70v9199/099l12 com'l only symbol parameter min.max.min.max.min.max.min.max.unit t cyc1 clock cycle time (flow-through) (2) 19 ____ 22 ____ 25 ____ 30 ____ ns t cyc2 clock cycle time (pipelined) (2) 10 ____ 12 ____ 15 ____ 20 ____ ns t ch1 clock high time (flow-through) (2) 6.5 ____ 7.5 ____ 12 ____ 12 ____ ns t cl1 clock lo w time (flo w-thro ug h) (2) 6.5 ____ 7.5 ____ 12 ____ 12 ____ ns t ch2 clock high time (pipelined) (2) 4 ____ 5 ____ 6 ____ 8 ____ ns t cl2 clock low time (pipelined) (2) 4 ____ 5 ____ 6 ____ 8 ____ ns t r clock rise time ____ 3 ____ 3 ____ 3 ____ 3ns t f clock fall time ____ 3 ____ 3 ____ 3 ____ 3ns t sa address setup time 3.5 ____ 4 ____ 4 ____ 4 ____ ns t ha address hold time 0 ____ 0 ____ 1 ____ 1 ____ ns t sc chip enable setup time 3.5 ____ 4 ____ 4 ____ 4 ____ ns t hc chip enable hold time 0 ____ 0 ____ 1 ____ 1 ____ ns t sw r/w se tup time 3.5 ____ 4 ____ 4 ____ 4 ____ ns t hw r/w ho ld time 0 ____ 0 ____ 1 ____ 1 ____ ns t sd input data setup time 3.5 ____ 4 ____ 4 ____ 4 ____ ns t hd input data hold time 0 ____ 0 ____ 1 ____ 1 ____ ns t sad ads setup time 3.5 ____ 4 ____ 4 ____ 4 ____ ns t had ads hold time 0 ____ 0 ____ 1 ____ 1 ____ ns t scn cnten setup time 3.5 ____ 4 ____ 4 ____ 4 ____ ns t hcn cnten hold time 0 ____ 0 ____ 1 ____ 1 ____ ns t srst cntrst setup time 3.5 ____ 4 ____ 4 ____ 4 ____ ns t hrst cntrst ho ld time 0 ____ 0 ____ 1 ____ 1 ____ ns t oe output enable to data valid ____ 6.5 ____ 7.5 ____ 9 ____ 12 ns t olz outp ut enab le to output low-z (1) 2 ____ 2 ____ 2 ____ 2 ____ ns t ohz outp ut enab le to output high-z (1) 17 17 17 17ns t cd1 clock to data valid (flow-through) (2) ____ 15 ____ 18 ____ 20 ____ 25 ns t cd2 clock to data valid (pipelined) (2) ____ 6.5 ____ 7.5 ____ 9 ____ 12 ns t dc data outp ut hold afte r clock hig h 2 ____ 2 ____ 2 ____ 2 ____ ns t ckhz clock hig h to outp ut hig h-z (1) 29292929ns t cklz clock hig h to outp ut lo w-z (1) 2 ____ 2 ____ 2 ____ 2 ____ ns port-to-port delay t cwdd write po rt clo ck hig h to read data de lay ____ 24 ____ 28 ____ 35 ____ 40 ns t ccs clock-to-clock setup time ____ 8 ____ 10 ____ 15 ____ 15 ns 4859 tbl 11
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 9 timing waveform of read cycle for flow-through output ( ft /pipe "x" = v il ) (3,6) timing waveform of read cycle for pipelined operation ( ft /pipe "x" = v ih ) (3,6) an an + 1 an + 2 an + 3 t cyc1 t ch1 t cl1 r/ w address data out ce 0 clk oe t sc t hc t cd1 t cklz qn qn + 1 qn + 2 t ohz t olz t oe t ckhz 4859 drw 06 (1) (1) (1) (1) (2) ce 1 t sw t hw t sa t ha t dc t dc (5) t sc t hc .. an an + 1 an + 2 an + 3 t cyc2 t ch2 t cl2 r/ w address ce 0 clk ce 1 (4) data out oe t cd2 t cklz qn qn + 1 qn + 2 t ohz t olz t oe 4859 drw 07 (1) (1) (1) (2) t sc t hc t sw t hw t sa t ha t dc t sc t hc (5) (1 latency) (6) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ads = v il , cnten and cntrst = v ih . 4. the output is disabled (high-impedance state) by ce 0 = v ih or ce 1 = v il following the next rising edge of the clock. refer to truth table 1. 5. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 6. 'x' here denotes left or right port. the diagram is with respect to that port.
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 10 timing waveform with port-to-port flow-through read (4,5,7) timing waveform of a bank select pipelined read (1,2) t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk 4859 drw 08 q 0 q 1 q 3 data out(b1) t ch2 t cl2 t cyc2 (3) address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) q 2 q 4 t cd2 t cd2 t ckhz t cd2 t cklz t dc t ckhz t cd2 t cklz (3) (3) t sc t hc (3) t ckhz (3) t cklz (3) t cd2 a 6 a 6 t dc t sc t hc t sc t hc data in "a" clk "b" r/ w "b" address "a" r/ w "a" clk "a" address "b" no match match no match match valid t cwdd t cd1 t dc data out "b" 4859 drw 09 valid valid t sw t hw t sa t ha t sd t hd t hw t cd1 t ccs t dc t sa t sw t ha (6) (6) notes: 1. b1 represents bank #1; b2 represents bank #2. each bank consists of one idt70v9199/099 for this waveform, and are setup for d epth expansion in this example. address (b1) = address (b2) in this situation. 2. oe and ads = v il ; ce 1(b1) , ce 1(b2) , r/ w , cnten , and cntrst = v ih . 3. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 4. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . 5. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 6. if t ccs < maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs > maximum specified, then data from right port read is not valid until t ccs + t cd1 . t cwdd does not apply in this case. 7. all timing is the same for both left and right ports. port "a" may be either left or right port. port "b" is the opposite fro m port "a".
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 11 timing waveform of pipelined read-to-write-to-read ( oe = v il ) (3) timing waveform of pipelined read-to-write-to-read ( oe controlled) (3) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 3. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . "nop" is "no operation". 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 4859 drw 10 qn qn + 3 data out ce 1 t cd2 t ckhz t cklz t cd2 t sc t hc t sw t hw t sa t ha t ch2 t cl2 t cyc2 read nop read t sd t hd (4) (2) (1) (1) t sw t hw write (5) r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 data in dn + 3 dn + 2 ce 0 clk 4859 drw 11 data out qn qn + 4 ce 1 oe t ch2 t cl2 t cyc2 t cklz (1) t cd2 t ohz (1) t cd2 t sd t hd read write read t sc t hc t sw t hw t sa t ha (4) (2) t sw t hw
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 12 timing waveform of flow-through read-to-write-to-read ( oe = v il ) (3) timing waveform of flow-through read-to-write-to-read ( oe controlled) (3) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 3. ce 0 and ads = v il ; ce 1 , cnten , and cntrst = v ih . "nop" is "no operation". 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 4859 drw 12 qn data out ce 1 t cd1 qn + 1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t cd1 t dc t ckhz qn + 3 t cd1 t dc t sc t hc t sw t hw t sa t ha read nop read t cklz (4) (2) (1) (1) t sw t hw write (5) r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 (4) data in dn + 2 ce 0 clk 4859 drw 13 qn data out ce 1 t cd1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t dc qn + 4 t cd1 t dc t sc t hc t sw t hw t sa t ha read write read t cklz (2) dn + 3 t ohz (1) (1) t sw t hw oe t oe
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 13 timing waveform of pipelined read with address counter advance (1) timing waveform of flow-through read with address counter advance (1) notes: 1. ce 0 and oe = v il ; ce 1 , r/ w , and cntrst = v ih . 2. if there is no address change via ads = v il (loading a new address) or cnten = v il (advancing the address), i.e. ads = v ih and cnten = v ih , then the data output remains constant for subsequent clocks. address an clk data out qx - 1 (2) qx qn qn + 2 (2) qn + 3 ads cnten t cyc2 t ch2 t cl2 4859 drw 14 t sa t ha t sad t had t cd2 t dc read external address read with counter counter hold t sad t had t scn t hcn read with counter qn + 1 address an clk data out qx (2) qn qn + 1 qn + 2 qn + 3 (2) qn + 4 ads cnten t cyc1 t ch1 t cl1 4859 drw 15 t sa t ha t sad t had read external address read with counter counter hold t cd1 t dc t sad t had t scn t hcn read with counter
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 14 address (4) an d 0 t ch2 t cl2 t cyc2 q 0 q 1 0 clk data in r/ w cntrst 4856 drw 17 internal (3) address ads cnten t srst t hrst t sd t hd t sw t hw counter reset write address 0 read address 0 read address 1 read address n qn an + 1 an + 2 read address n+1 data out (5) t sa t ha 1 an an + 1 (6) ax t sad t had t scn t hcn (6) timing waveform of write with address counter advance (flow-through or pipelined outputs) (1) timing waveform of counter reset (pipelined outputs) (2) address an clk data in dn dn + 1 dn + 1 dn + 2 ads cnten (7) t ch2 t cl2 t cyc2 4856 drw 16 internal (3) address an (7) an + 1 an + 2 an + 3 an + 4 dn + 3 dn + 4 t sa t ha t sad t had write counter hold write with counter write external address write with counter t sd t hd notes: 1. ce 0 and r/ w = v il ; ce 1 and cntrst = v ih . 2. ce 0 = v il ; ce 1 = v ih . 3. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 6. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset cycle. addr 0 will be accessed. extra cycles are shown here simply for clarification. 7. cnten = v il advances internal address from ?an? to ?an +1?. the transition shown indicates the time required for the counter to advance. the ?an +1? address is written to during this cycle.
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 15 depth and width expansion the idt70v9199/099 features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no require- ments for external logic. figure 4 illustrates how to control the varioius chip enables in order to expand two devices in depth. the idt70v9199/099 can also be used in applications requiring expanded width, as indicated in figure 4. since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 18/16-bit or wider applications. 4859 drw 18 idt70v9199/099 ce 0 ce 1 v dd control inputs ce 1 ce 0 control inputs ce 0 ce 1 a 17 ce 1 ce 0 idt70v9199/099 control inputs control inputs cntrst clk ads cnten r/ w oe v dd idt70v9199/099 idt70v9199/099 figure 4. depth and width expansion with idt70v9199/099 functional description the idt70v9199/099 provides a true synchronous dual-port static ram interface. registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. all internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the low to high transition of the clock signal. an asynchronous output enable is provided to ease asynchronous bus interfacing. counter enable inputs are also provided to staff the operation of the address counters for fast interleaved memory applications. ce 0 = v il and ce 1 = v ih for one clock cycle will power down the internal circuitry to reduce static power consumption. multiple chip enables allow easier banking of multiple idt70v9199/099's for depth expansion con- figurations. when the pipelined output mode is enabled, two cycles are required with ce 0 = v ih or ce 1 = v il to re-activate the outputs.
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 16 ordering information note: 1. industrial temperature range is available. for specific speeds, packages and powers contact your sales office. a power 99 speed a package a process/ temperature range blank i (1) commercial (0 cto+70 c) industrial (-40 cto+85 c) pf 100-pin tqfp (pn100-1) 6 7 9 12 xxxxx device type idt speed in nanoseconds 4859 drw 19 llowpower 70v9199 70v9099 1152k (128k x 9-bit) synchronous dual-port ram 1024k (128k x 8-bit) synchronous dual-port ram commercial only commercial only commercial & industrial commercial only . idt dual-port part number dual-port i/o specitications dual-port clock specifications idt pll clock devices idt non-pll clock devices voltage i/o input capacitance input duty cycle requirement maximum frequency jitter tolerance 70v9199/099 3.3 lvttl 9pf 40% 100 150ps idt2305 idt2308 idt2309 fct3805 fct3805d/e fct3807 fct3807d/e 4859 tbl12 idt clock solution for idt70v9199/099 dual-port
6.42 idt70v9199/099l high-speed 3.3v 128k x9/x8 dual-port synchronous pipelined static ram industrial and commercial temperature ranges 17 datasheet document history 9/30/99: initial public release 11/12/99: repl aced idt logo 01/10/01: page 3 changed information in truth table ii page 4 increased storage temperature parameters clarified t a parameter page 5 dc electrical parameters?changed wording from "open" to "disabled" changed 200mv to 0mv in notes removed preliminary status 04/09/03: consolidate multiple devices into one datasheet changed naming conventions from v cc to v dd and from gnd to v ss page 2 & 3 added date revision to pin configurations page 5 added junction temperature to absolute maximum ratings table added ambient temperature footnote page 1, 6 & 16 added 6ns speed grade page 6 added updated dc power numbers to the dc electrical characteristics table page 8 added 6ns speed ac timing numbers and changed t oe to be equal to t cd2 in the ac electrical characteristicstable page 16 added idt clock solution table the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dual porthelp@idt.com www.idt.com

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